1. Field of the Invention
This invention relates to a lightly doped drain (LDD) MOS device and, more particularly, to an LDD MOS device having an element separation region having an electrostatic screening electrode.
1. Description of the Background Art
The LDD MOS transistor is disclosed in a Japanese Patent Laying Open No. 62-241375, No. 62-33470 and "Fabrication of High-Performance LDDFET'S with Oxide Sidewall-Spacer Technology" IE.sup.3 TRANSACTIONS ELECTRON DEVICE, Vol. ED-29, No. 4, April 1982, pp. 590-596.
FIG. 1 shows an LDD MOS transistor disclosed in this gazette or publication and forming the background of the present invention. In FIG. 1, a gate electrode 2 is formed through a gate insulating film 3 on a planar surface of a P-type semiconductor substrate. A sidewall or a sidewall insulating film 4 is formed in contact with each sidewall of this gate electrode 2. A pair of N-type first diffusion layers 5a and 5b forming source and drain region are formed on a planar surface of the semiconductor substrate 1 on both sides of the gate electrode 2 so that one end of each of the layers 5a and 5b is overlapped with the side section of the gate electrode. A pair of N-type second diffusion layers 6a and 6b forming source and drain regions are formed on the above planar surface of the semiconductor substrate 1 on both sides of the gate electrode 2 so that one end of each of the layers 6a and 6b is overlapped with the side section of said sidewall insulating film 4 but is not overlapped with the gate electrode 2. These second diffusion layers 6a and 6b are the diffusion layers in which the impurities are diffused at a higher concentration than in the first diffusion layers 5a and 5b. The N-type diffusion layers 5a, 5b, 6a and 6b, surface regions of the p-type semiconductor substrate between the diffusion layers 5a and 6a and the diffusion layers 5b and 6b, the gate insulating film on the surface region and the gate electrode on the gate insulating film constitute a P-type field effect transistor.
In an element isolation region 7, a selective oxide film 8 is formed by a LOCOS method (Method of Local Oxidation of Silicon), and a P-type impurity diffusion layer 9 is formed below the selective oxide film 8 for preventing field inversion of the element separation region 7. The numeral 10 denotes an element forming region including source and drain regions and a gate electrode.
The operation of the above described P-type field-effect transistor is explained below. FIG. 2A is a sectional view of the LDD MOS transistor of FIG. 1, looking in the direction shown by an arrow mark Y. In FIG. 2A, when the potential of the source region 6a is fixed, the voltage (+) is applied to the drain region 6b, the potential (-) is applied to the semiconductor substrate and the potential (+) is applied to the gate electrode 2 to operate this transistor, the electrons, produced in an inversion layer in response to the gate voltage, and acting as carriers, are migrated toward the drain as indicated by the arrow mark Id due to the electrical field between the source and the drain regions.
Referring to FIG. 2B, in the case of a transistor or an ordinary MOS transistor other than LDD type transistor, in which the impurity diffusion layer 6b' of the drain region is not formed by impurities of the lower concentration, but by impurities of the higher concentration, and this high concentration impurity region 6b' is overlapped with the gate electrode 2, the electrical field produced in the vicinity of the drain region 6b` becomes stronger as the distance between the source region 6a` and the drain region 6b` becomes shorter with reduction in size of the transistor. Thus, in such a case, the carrier electrons collide against the atoms within the semiconductor substrate 1 within a drain depletion region 11 produced by this electrical field, to cause ionization to produce electron-positive hole pairs. Among these electron-positive hole pairs, those electrons having an energy in excess of the potential barrier of a approximately 3.1eV presented by the interface between Si substrate 1 and SiO.sub.2 insulating layer 3, are turned into hot electrons and injected into a silicon oxide film 3. A portion of the injected electrons are captured in the oxide film and act as electrical charges to produce the effect of increasing the gate threshold voltage of the transistor. This results in deteriorated characteristics and operational reliability of the transistor.
For preventing the lowering of the operational reliability and the deterioration of the characteristics of the transistor, there is known an LDD MOS transistor shown in FIGS. 1 and 2A in which the impurity diffusion layer 5b has a low impurity concentration. That is, the impurity concentration of the drain region 5b overlapped with the gate electrode for reducing the electrical field in the vicinity of the drain regions 5b and 6b to prevent hot electrons from being produced.
However, in the conventional LDD MOS transistor, the process of element separation is performed by the LOCOS method, so that, as shown in FIG. 3, which is a sectional view of the transistor seen from the direction X in FIG. 1, when the selective oxidation film 8 is oxidized at higher temperatures, the P-type impurities 14 are introduced by diffusion, as shown by arrow marks in FIG. 3, from the P-type impurity diffusion layer 9 provided below the selective oxide film 8 into source and drain impurity diffusion layers 5a, 5b, 6a, 6b and into a channel 17 of the transistor. In FIG. 3, a region shown by a broken line 15 represents a region into which the impurities are intruded. As a result of the introduction of impurities, the concentration of the impurities is increased at the boundary between the element forming region 10 and the element separation region 7 and, above all, at a channel boundary region in the vicinity of the LDD structure 16 of the transistor, to cause an increase in the gate threshold voltage, known as the narrow channel effect, so that the advantages of employing the LDD structure in the drain of the transistor cannot be exploited efficiently. This effect becomes most evident particularly when the channel length of the LDD MOS transistor is less than 1 micron.
In the above described LDD MOS transistor, when the channel length becomes smaller than 1 micron, the effect of intrusion of impurities from the element separation region into the element forming regions becomes conspicuous with the result that the advantages of employing the LDD structure in the drain cannot be exploited sufficiently and hence the characteristics and the operational reliability of the transistor cannot be maintained.
It should be noted that the above, background isolation structure uses an insulator to provide isolation between devices, an isolation structure using a conductor held at a potential below a threshold which permits conductivity between FET devices such as is disclosed in U.S. patent application Ser. No. 376,660 filed on July 7, 1989 by Wakamiya et al. assigned to Mitsubishi Denki Kabushiki Kaisha. However, such isolation has not been used in combination with LDE structures having the known advantages of such devices and particularly at the short channel lengths to which this invention is directed. This combination including an LDI; structure provides the additional advantage of permitting further reduction in transistor size by reduction of channel width in a manner which is consistent with avoidance of the narrow channel effect, as described above.